Synchronous memory performs access operations based on a clock signal as a timing reference to enable the transmission and reception of data with a known relationship to the reference. I/O (input/output) interfaces for synchronous interconnections commonly use a DLL (delay locked loop) to maintain the known relationship with respect to the reference timing. DLL circuits adjust the timing of internal signals to align with the timing reference. Synchronous operation can improve signaling between connected devices. However, DLL operation traditionally involves continuous tracking of the reference timing signal when the DLL is active, which consumes a significant amount of power. DLL tracking can be referred to as DLL calibration, which the phase control is calibrated to the external reference timing. The power consumption of continuous DLL calibration can consume a significant portion of the overall power budget in systems designed to operate in low power modes.
It will be understood that depending on the application of the memory device, the signaling speed can be lower or higher. For lower power applications, typically the signaling speeds are lower. The DLL timing compensation adjusts timing characteristics that affect a data “eye” that identifies a threshold for signaling by the memory device. Continuous DLL tracking maintains narrow margins on the data eye. Lower speed signaling can tolerate higher variance in the margins of the data eye, and DLL calibration may not be required in some implementations. Higher speed signaling may require continuous DLL calibration to ensure the data eye margins required for higher speed operation. Traditionally, manufacturers and system designers either have DLL calibration continuously operating when the DLL is active, or do not include it.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.